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SanDisk Industrial Grade CompactFlash 5000 Product Manual
© 2007 SanDisk® Corporation 14 March 2007
Table 10: Signal Description
Signal Name Dir. Pin Description
A10-A0 (PC Card Memory
Mode) (PC Card I/O Mode)
A2-A0 (True IDE Mode) A10-
A3 (True IDE Mode)
I I 8, 10, 11, 12,
14, 15, 16, 17,
18, 19, 20 18,
19, 20
These address lines, along with the -REG signal, are used to select the following: I/O and memory-mapped
port address registers within the card, a byte in the card's information structure and its configuration control and
status registers. In True IDE Mode only A[2:0] is used to select one of eight registers in the Task File. In True
IDE Mode these remaining address lines should be grounded by the host.
BVD1 (PC Card Memory
Mode) -STSCHG (PC Card
I/O Mode) -PDIAG (True IDE
Mode)
I/O 46 This signal is asserted high as the BVD1 signal since a battery is not used with this product. The Status
Changed signal is asserted low to alert the host to changes in the RDY/-BSY and Write Protect states, while
the I/O interface is configured. Its use is controlled by the Card Config. and Status Register. In True IDE Mode,
this input/output is the Pass Diagnostic signal in the master/slave handshake protocol.
BVD2 (PC Card Memory
Mode) -SPKR (PC Card I/O
Mode) -DASP (True IDE
Mode)
I/O 45 This output line is always driven to a high state in Memory Mode since a battery is not required for this product,
as well as in I/O Mode, since this product does not support the audio function. In True IDE Mode, this
input/output is the Disk Active/Slave Present signal in the master/ slave handshake protocol.
-CD1, -CD2 (PC Card Memory
Mode) (PC Card I/O Mode)
(True IDE Mode)
O 26, 25 These Card Detect pins are connected to ground on the card. The host uses these pins to determine if the card
is fully inserted into its socket.
-CE1, -CE2 (PC Card Memory
Mode) (PC Card I/O Mode) -
CS0, -CS1 (True IDE Mode)
I 7, 32 The Card Enable input signals are used both to select the card and to indicate to the card whether a byte or a
word operation is being performed. -CE2 always accesses the odd byte of the word. -CE1 accesses either the
even or the odd byte of the word, depending on A0 and -CE2. A multiplexing scheme based on A0, -CE1, -CE2
allows 8 bit hosts to access all data on D0-D7. In True IDE Mode, -CS0 is the chip select for the Task File
registers, while -CS1 is used to select the Alternate Status Register and the Device Control Register.
-CSEL (PC Card Memory
Mode) (PC Card I/O Mode)
I 39 This signal is not used for PC Card Memory Mode or PC Card I/O Mode.
-CSEL (True IDE Mode) This internally pulled up signal is used to configure the device as a master or slave when configured in True
IDE Mode. When this pin is grounded, the device is configured as a master. When the pin is open, this device
is configured as a slave.
D15-D00 (PC Card Memory
Mode) (PC Card I/O Mode)
D15-D00 (True IDE Mode)
I/O 31, 30, 29, 28,
27, 49, 48, 47,
6, 5, 4, 3, 2,
23, 22, 21
These lines carry the data, commands and status information between the host and the controller. D00 is the
LSB of the word’s even byte; D08 is the LSB of the word’s odd byte. In True IDE Mode, all Task File operations
occur in byte mode on the low order bus D00D07 while all data transfers are 16 bits using D00-D15.
GND (PC Card Memory
Mode) (PC Card I/O Mode)
1, 50 Ground.
- SanDisk Industrial Grade 1
- CompactFlash 5000 1
- Table of Contents 2
- List of Tables 5
- Introduction 8
- Features 9
- CompactFlash Standard 10
- PCMCIA Standard 10
- Related Documentation 10
- Functional Description 10
- Technology Independence 11
- Defect and Error Management 11
- Bad Block Management 12
- Automatic Sleep Mode 12
- Power Supply Requirements 12
- Wear Leveling 12
- Product Specifications 14
- System Power Requirements 15
- System Performance 15
- System Reliability 16
- Physical Specifications 16
- Regulatory Compliance 17
- Traceability 17
- Interface Description 18
- Electrical Description 20
- Table 10: Signal Description 21
- Electrical Specification 24
- Output Drive Characteristics 25
- Power Up/Down Timing 26
- Common Memory Read Timing 27
- Table 16 (continued) 28
- Memory Timing Diagrams 29
- I/O Read Timing Diagram 30
- True IDE Mode 32
- Card Configuration 35
- Attribute Memory Function 36
- Attribute Memory function 37
- Attribute Memory) 38
- 202h in Attribute Memory) 39
- Memory) 40
- I/O Transfer Function 41
- Configurations 43
- Memory Mapped Addressing 45
- True IDE Mode Addressing 46
- ATA Registers 46
- Read Only) 47
- Device Control Register 50
- Offset Fh) 50
- ATA Command Description 52
- Check Power Mode–98H, E5H 53
- Erase Sector(s)–C0H 54
- Format Track–50H 55
- Identify Device–ECH 55
- Idle–97H, E3H 63
- Idle Immediate–95H, E1H 63
- Read Buffer–E4H 64
- Read DMA Command–C8H, C9H 64
- Read Multiple–C4H 65
- Read Long Sector–22H, 23H 66
- Read Sector(s)–20H, 21H 66
- Recalibrate–1XH 67
- Request Sense–03H 67
- Seek–7XH 68
- Set Features–EFH 69
- Set Multiple Mode–C6H 70
- Set Sleep Mode–99H, E6H 70
- Standby–96H, E2H 71
- Standby Immediate–94H, E0H 71
- Translate Sector–87H 72
- Wear Level–F5H 72
- Write Buffer–E8H 73
- Write DMA Command–CAH, CBH 73
- Write Long Sector–32H, 33H 73
- Write Multiple Command–C5H 74
- Write Sector(s)–30H, 31H 75
- Write Verify Sector(s)–3CH 76
- Error Posting 77
- CIS Description 78
- I. Warranty Statement 95
- II. General Provisions 95
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